VLSI technology is currently dealing with a serious challenge, as the exponential growth of density in VLSI and CMOS chips has reached its limit. Power dissipation in VLSI chip refers to heat generation, which is a real barrier against traditional CMOS technology. IrReversible logic leads to problems such as energy dissipation, heat generation, information loss and slow computations. We need a new technology for solving these problems. Using Reversible logic can help solve this problem. In next generation of optical computers, electrical circuits and wires will be replaced by several optical fibers and these systems will be more efficient because they will be cheaper, lighter, and more compact without interference. Based on optical computations, several optical switches have been proposed for future applications. One of these switches is the Mach-Zehnder switch. Its behavior and the Reversible circuits, which can be made with this switch is studied in this article. Finally, we introduce and design three new all-optical Reversible gates named NFT, SRK and MPG, which are effective in designing all-optical Reversible logical circuits such as flip-flops and other all-optical Reversible sequential circuits. We also simulate one all-optical Reversible circuits implemented with Mach-Zehnder switch and provide simulation challenges and solutions to overcome these challenges.

Quantum-dot Cellular Automata (QCA) is an emerging and promising technology that provides significant improvements over CMOS. Recently QCA has been advocated as an applicant for implementing Reversible circuits. However QCA, like other Nanotechnologies, suffers from a high fault rate. The main purpose of this paper is to develop a fault tolerant model of QCA circuits by redundancy in hardware and also identifying the faulty module by a proposed Reversible QCA comparator circuit. Triple Module Redundancy (TMR) mechanism is implemented for Reversible QCA circuits to make them more Reliable. Our proposed Comparator and Detector design uses the minimum number of clocking zones and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells. QCA Designer ver.2.0.3 is used for simulation and verifying the design.

Reversible logic is a new technology that is considered as an essential requirement for the design of quantum computers. In the calculation unit of computers, multiplication is one of the most frequently used operations. In this paper, we propose new optimized algorithms to design a parity-preserving Reversible Vedic multiplier. Three approaches for designing optimized Reversible Vedic multiplier circuits are proposed which are better than the existing circuits in terms of quantum cost, number of garbage outputs, number of constant inputs, and other criteria. The proposed Reversible Vedic multipliers can be generalized to produce parity-preserving n*n Reversible multiplier. We have also achieved some relations which can calculate the quantum cost, the number of constant inputs, and the number of required garbage outputs for the proposed Vedic circuit of any dimension. We have shown that our proposed Reversible Vedic multiplier in n*n scale is the best compared to the existing Vedic multipliers.

Efficient distribution of service requests between fog and cloud nodes considering user mobility and fog nodes’ overload is an important issue of fog computing. This paper proposes a heuristic method for task placement considering the mobility of users, aiming to serve a higher number of requested services and minimize their response time. This method introduces a formula to overload prediction based on the entry-exit ratio of users and the estimated time required to perform current requests that are waiting in the queue of a fog node. Then, it provides a solution to avoid the predicted overloading of fog nodes by sending all delay-tolerant requests in the overloaded fog node’s queue to the cloud to reduce the time required for servicing delay-sensitive requests and to increase their acceptance rate. In addition, to prevent requests from being rejected when the mobile user leaves the coverage area of the current fog node, the requests in the current fog node’s queue will be transferred to the destination fog node. Simulation results indicate that the proposed method is effective in avoiding the overloading of the fog nodes and outperforms the existing methods in terms of response time and acceptance rate.

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of Reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 design is proposed for the test layer implementation regarding to overhead and power savings. Our proposed Reversible QCA MUX 2×1 design resulted in decrease in QCA cell counts and minimal input to output delay. The proposed design is simulated and verified using QCA Designer ver.2.0.3.

One of the major challenges and constraints in designing very large integrated circuits is the power dissipation of transistors. Reversible logic is one of the new paradigm in reducing the power consumption of digital circuits in the quantum computing field. In this paper, an improved design of a parallel 5-bit parity preserving Reversible signed multiplier circuit is presented. Reversible circuit designs with parity preserving property are an important issue for the implementation of fault tolerant systems in nanotechnology area. To design of the proposed multiplier, the Reversible full adder circuit using 5×5 Reversible HBF block with low quantum cost, and the 4×4 Reversible HBL gate, with parity preserving property are proposed. The structure of the multiplier circuit consists of two parts of the partial product generation (PPG) and multi-operand addition (MOA). This structure is based on Baugh-Wooley and Wallace-Tree algorithms, which results in improved speed of operation in a 5-bit multiplier for signed digits. The proposed circuits are optimized based on important evaluation issues such as quantum cost, garbage outputs and constant inputs, and also are compared with the existing circuits. The main goal is to reduce the quantum cost, the number of constant inputs and garbage outputs in the design of the proposed multiplier circuit. The results of the final evaluation and comparison shows that the proposed multiplier in this study is improved by 26% in quantum cost, 9% in garbage outputs and 9% in constant inputs relative to the best existing designs.